AgilA32 Simulator
The chip's own Verilog (RV32I CPU and two-state-machine PIO), compiled to WebAssembly and running in this page. Chip clock 24 MHz; the simulation itself runs slower than real time.
AgilA32 on GitHub: github.com/alexandercoabad/AgilA32_PIO- RV32I CPU
- 2 PIO state machines
- 24 MHz
- IHP CMOS5L
- Tiny Tapeout 8x4 tiles
Built for the Jane Street protocol-emulator ASIC competition: a small RISC-V core plus RP2040-style PIO that firmware turns into UART, SPI, I2C and other protocols after fabrication.
Board
Scenario
Status
- State
- loading
- Clocks
- 0
- Chip time
- 0 µs
- Sim speed
- -
Waveform
Scroll to zoom, drag to pan. The time axis is in chip clocks; the label shows microseconds at 24 MHz. The orange outline on PAD 8 and PAD 9 marks the span where the chip drives the pad.
Block diagram (live)
Redrawn from the block diagram in the project documentation. Highlighted blocks are in use: the memory block that holds the current instruction, the target of a load or store (worked out from the instruction and its base register), the QSPI engine while a chip-select is low, and each PIO state machine when its program counter moves. The little circles are the ten PIO pins; a ring means the PIO drives that pin.
Checks
Processor state
PIO state machine 0
PIO state machine 1
PIO pin outputs