Cycle-accurate model of tt_um_mc14500b_soc_extended (1-bit ICU, 64-byte program RAM, free-running PC, edge detector, clock divider, output shift latch) with runnable examples. Chip design: github.com/alexandercoabad/MC14500B_IHP · Tiny Tapeout page.
uo_out[7:0] (brightness = fraction of time high, like persistence of vision)
ui_in[0] feeds the rising-edge detector (address 8). ui_in[7:5] are read at addresses D/E/F, one clock late. ui_in[4:1] are not connected to the core.
Orange is the 1-bit data path. Solid: the read mux picks one bit (from the 8-bit scratch RAM, the 3-bit input latch, the two 1-bit flags, or bit 0 of the output latch), IEN masks it and the 1-bit ALU updates RR. Dashed: on STO/STOC, RR (or its inverse) is written back through the OEN gate to the scratch RAM, the edge flag, the SLOW flag or the output latch. Highlighted blocks are the ones the current instruction reads (operand address) or writes. The divider also stays outlined while the SLOW flag is 1, because it is then gating the PC (gray arrow). The output latch stays outlined for 0.3 s after each bit is shifted into it, the edge detector while its flag is 1 and for 0.3 s after the flag changes, and the input latch for 0.3 s after the sampled switches change. Values update every frame. This is the data path of project.v: the operand selects one bit through the read mux, IEN masks it, the ALU updates RR, and OEN/skip/done gate the write.
Mnemonics: NOP LD LDC AND ANDC OR ORC XNOR STO STOC IEN OEN JMP SKZ NOPE NOPF. Operands: 0–15 or R0–R7, EDGE(8), SLOW(9), ZERO(A), OUT(C), IN5/IN6/IN7(D/E/F). Padded with NOP to 64 bytes. rst_n also clears program RAM, so Assemble & run does reset → program mode writes → run.