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If you have done the ReRAM lessons, you already know a cell whose conductance is a stored weight. A phase-change memory (PCM) cell does the same job with different physics. A ReRAM cell is pushed around by an electric field that moves ions and builds or dissolves a filament, so SET and RESET are opposite-polarity pulses. A PCM cell is changed by heat: a short, strong pulse melts a tiny region into a glass-like state that blocks current, and a longer, gentler pulse lets it crystallize again. Both keep their value with the power off, but PCM’s value drifts, its RESET is abrupt, and it needs far more current to write. This page puts the two cells side by side before you meet the PCM array. New to ReRAM? Do its Step 1 first.
A thin layer of a chalcogenide alloy, for example germanium-antimony-tellurium (Ge₂Sb₂Te₅, called GST), sits on top of a small metal heater. The alloy has two solid phases. In the crystalline phase the atoms are lined up and the material conducts well (low resistance, LRS). In the amorphous phase the atoms are jumbled like glass and it conducts poorly (high resistance, HRS). A RESET pulse is short and strong: it melts a small dome of alloy over the heater, and the dome cools so fast that the atoms freeze in disorder. A SET pulse is longer and gentler: it holds the dome hot, but below the melting point, long enough for the atoms to line up again. A read at low voltage does not heat the cell enough to change anything, so within that read range it behaves like a resistor with whatever value was last written. That is the assumption behind the crossbar math in the simulator.
Melt sugar and cool it fast and you get clear glass (candy). Keep it warm and it slowly turns into crystals (rock candy). A PCM cell does the same with a blob of alloy about a hundred nanometres across, using heat from an electrical pulse instead of a stove. Glass blocks current, crystal passes it.
A ReRAM cell is a dimmer you can push up with a positive pulse and pull down with a negative one, in small steps either way. A PCM cell is a dimmer where turning it up is gentle (small SET pulses, one step at a time), but turning it down means one big pulse that switches it fully off, and then you climb again. Both stay where you left them with the house power cut, but the PCM one fades a little with time.
Conductance is the weight. Voltage is the input. Ohm's law (I = V·G) does the multiply, and the wire does the add. The weight is the physical state of the device, so it never has to be fetched. The catch: the state is set by heat, so writing is slow and costly, and the stored conductance drifts.
PCM means phase-change memory, also written PRAM or PCRAM (phase-change RAM). Phase change: the value is stored in which solid phase a small region of the alloy is in, not as charge on a capacitor or a floating gate. The two phases differ in resistance by a factor of 100 or more.
It is also non-volatile: the phase stays when the power is off.
Use two states. The amorphous state (HRS) stands for one bit value and the crystalline state (LRS) for the other. Which is 0 and which is 1 is a convention.
Write: a RESET or SET pulse. Read: apply a small voltage, well below the voltage that would start to heat the cell, and compare the current with a reference.
Only the gap between the two states matters, so a fair amount of variation is tolerable. Drift slowly widens the gap, which is harmless for a bit.
A neural-network layer is a set of weighted sums: each output adds up the inputs multiplied by weights, then applies a simple nonlinear step.
Here the cell stores a weight, not a bit, and its conductance is set to one of many levels between the two extremes. Drive the rows with input voltages. Each cell gives I = V·G and each bit line adds the currents, so the whole sum is one read. The nonlinear step happens outside the array. This is the crossbar of Steps 2 and 3. IBM Research has built chips that work this way (see Le Gallo et al. under Further reading).
Same device, different demands. As memory, one row is read at a time and only the gap between two states matters. As weights, every row is driven at once and the accuracy of every conductance matters, so variation, drift and write precision become the main problems. Drift is the one that sets PCM apart. That is why Step 2 is about writing a weight precisely.
Why this alloy? GST sits on the line between germanium telluride and antimony telluride and is the best-known phase-change material. It crystallizes in tens of nanoseconds, which is what makes a nanosecond-scale SET pulse possible, and both phases are stable for years at room temperature. The same family of alloys is used in rewritable optical discs, where a laser does the heating (see Wuttig and Yamada under Further reading).
What the heater does. The pulse does not move ions the way it does in ReRAM. It pushes current through a narrow heater, and Joule heating warms the alloy right above it. That is why the cell in section 1 is drawn as a mushroom: a wide layer of alloy with a small heater contact below it, and an amorphous dome growing from the heater tip.
Two temperatures matter. The crystallization temperature (roughly 150 to 200 °C in GST) is where the atoms become mobile enough to line up. The melting point (about 600 °C) is where the crystal turns to liquid. A SET pulse aims for the range between them. A RESET pulse aims above the melting point and then cools the liquid in a few nanoseconds, too fast for crystals to form.
Threshold switching. A fresh amorphous cell barely conducts at low voltage, yet above a threshold voltage (Vth) it suddenly snaps into a conductive state, with no phase change yet. That is what lets enough current flow to heat the dome in the first place. Section 3 shows it.
The simulator is generic. Its numbers, such as the 0.5 to 50 µS range, the temperatures and the pulse lengths, are illustrative and not measured on a specific device.
Both cells below start in a high-resistance state. Send the same pulses to both: the page sends your SET to the ReRAM cell as a positive pulse and your RESET as a negative one, because that is how ReRAM works. Watch how each reacts to the same amplitude. Then try cutting the power, and letting time pass.
Is a SET pulse the same as a RESET pulse? No, but not because of polarity. In PCM the heat does the work, so both pulses have the same polarity (the cell is unipolar) and go through the same heater. They differ in amplitude, width and trailing edge. The graph below the two cells shows the temperature each pulse gives the dome. Peak below the crystallization temperature: nothing happens. Peak between the two temperatures: the dome crystallizes (SET). Peak above the melting point and a sharp trailing edge: the dome re-forms as glass (RESET).
Opposite pictures, same electrical result. In PCM the thing that grows is the amorphous dome, which blocks current, so SET shrinks it (G goes up) and RESET grows it (G goes down). In ReRAM the thing that grows is the filament, which carries current, so SET grows it (G goes up) and RESET dissolves it (G goes down). Dome growth and filament growth are inverse, but SET raises conductance in both cells and RESET lowers it in both.
| SET | RESET | |
|---|---|---|
| Polarity across the cell | Same as RESET | Same as SET (unipolar) |
| Pulse shape | Moderate amplitude, longer (tens to hundreds of ns) | Higher amplitude, shorter (a few to tens of ns) |
| Peak temperature | Between the crystallization temperature and the melting point | Above the melting point |
| Trailing edge | Not critical | Must be sharp, so the melt freezes before crystals can grow |
| What happens | Atoms line up: the amorphous dome shrinks, crystal grows in from its edge | The region over the heater melts and freezes as glass: the dome re-forms |
| Resistance | Falls (G rises), a bit more with every pulse | Rises (G falls), most of the way in a single pulse |
| Current needed | Moderate | The largest current in the cell, which sets the size of the access transistor |
| What sets the level | Amplitude, width, number of pulses | Mostly amplitude: just above the melting point gives a small dome, higher gives a bigger one |
Same amplitude, different physics. The ReRAM cell ignores pulse width and trailing edge in this model: only the amplitude and the polarity matter, and it starts to switch above 0.8 V. Send a big SET pulse (above about 2.5 V) to both cells. The ReRAM filament simply grows more. The PCM dome melts, and the cell ends up more amorphous, as if it had been RESET. The SET and RESET graph above is drawn live from the sliders. Pulses that stay below the crystallization temperature do nothing. Reading above about 1 V starts to heat the cell, which is called read disturb. A slow trailing edge on a melting pulse lets the melt crystallize, so a RESET-sized pulse can act as a SET. This is the usual unipolar picture (for example Ge₂Sb₂Te₅). The model is illustrative: the dome heats as T = 27 °C + 162 K per V² × V² × (1 − e−t/30 ns), crystal growth is fastest near 430 °C, and none of the numbers are fitted to a real device. The next section shows how single pulses add up to a weight and where the pulse is applied in an array.
One gentle SET pulse shrinks the amorphous dome only a little, so the conductance climbs in steps. Writing a weight means stopping on the right rung. But the ladder only works in one direction. RESET does not walk back down one rung at a time: the melt-quench rebuilds the whole dome in one go. To lower a weight you either RESET and climb again, or let a second cell take the other side of a differential pair. The simulator’s write loop therefore erases first, then sends SET pulses and reads the cell back after each one.
The dome shrinks in equal steps, but conductance changes by a constant factor per rung (×2.2 here), not a constant amount, because current has to pass through the glass and its resistance grows exponentially with its thickness. The last rung is therefore a big jump in G and the first rung is a tiny one. That non-linear ladder is why PCM weight levels are not evenly spaced in conductance. The long red curved arrow along the bottom is the RESET: it jumps from the fully crystalline end straight back to the fully amorphous end in one step, instead of walking down the rungs. The dashed box marks where the cell in section 1 is now.
The pulse always goes through the heater of the one cell you want to change, and what you get depends on its amplitude and width. In an array you reach that cell through the wires and, almost always, an access device. Choose the pulse type and how the cell is wired:
A ReRAM cell draws a hysteresis loop through zero: sweep up past its SET voltage and the filament forms, so the current climbs smoothly and stays high on the way back, and a negative sweep past its RESET voltage flips it back (see the I-V loop in the ReRAM lesson). A PCM cell is different. It is unipolar, and its amorphous state conducts almost nothing until the voltage reaches a threshold voltage (Vth). Then the cell snaps into a conductive ON state and the current jumps by about two orders of magnitude (in a real circuit with a current limit, the voltage across the cell would also fall back towards the hold voltage). That current heats the dome. Slow voltage sweeps cool slowly, so the dome crystallizes on the way back and the cell ends up in the low-resistance state. Both axes are logarithmic because the PCM states differ by 100×. The shaded band is the read range. Only the positive half is drawn, so the green ReRAM trace shows just its SET half; its RESET half needs negative voltage.
Drag the slider yourself and notice that the order matters: the same voltage gives a very different current before and after the snap. Negative voltages behave the same way for PCM (the cell is unipolar), so only the positive half is drawn. Both cells start in their high-resistance states and receive the same voltage path. The pale lines show the two extreme states (the low-resistance and high-resistance branches) and the ON branch. The ON-state numbers are illustrative: a 5 kΩ series resistance, a 0.5 V offset and a 0.6 V hold voltage. Vth rises with the thickness of the dome (0.6 V + 0.7 V × amorphous fraction here, so a fully amorphous cell snaps at 1.3 V).
Sixteen cells were written to each of five targets: ReRAM in its low- and high-resistance states, and PCM crystalline, mid-level and fully amorphous. Both technologies scatter (variation), but not in the same way. PCM scatter grows towards the amorphous end, its conductance drifts down as a power law (faster the more amorphous the cell), and after very many cycles some cells get stuck. ReRAM’s two states scatter about equally, relax slowly towards the middle, and lose their gap after many cycles. Move the sliders.
Illustrative numbers, not measurements of a specific device. Drift follows G(t) = G(1 s) × (t / 1 s)−ν, with ν about 0.005 for crystalline cells and about 0.1 for fully amorphous ones, and ν itself varies from cell to cell. Hollow dots are PCM cells that wore out and stuck in the wrong state, which this model starts to do above about 108 cycles. The ReRAM rows use the same model as the ReRAM lesson: drift pulls both states towards the middle (by up to about a third), and the gap closes above about 106 cycles. Real endurance depends heavily on the material stack, so the ordering of the two technologies here is not a general ranking. The point is the shape of each effect, not the exact values.
| ReRAM cell | PCM cell | |
|---|---|---|
| What stores the value | A conductive filament of oxygen vacancies in a metal oxide | The phase of a small region of chalcogenide alloy: crystalline or amorphous |
| What changes it | An electric field that moves ions | Heat: Joule heating from the pulse current |
| Pulse polarity | Bipolar: SET is one polarity, RESET the opposite | Unipolar: SET and RESET have the same polarity and differ in amplitude, width and trailing edge |
| Writing up and down | Both directions can be gradual: more filament, less filament | Gradual one way (SET crystallizes a bit per pulse), abrupt the other (RESET melts the whole dome at once) |
| Write current and energy | Lower: the field does the work, though a SET needs a current limit | Highest: a RESET has to melt the alloy, which sets the size of the access transistor |
| Resistance window (in these models) | About 20× (5 to 100 µS) | About 100× (0.5 to 50 µS) |
| I-V curve | Hysteresis loop through zero, smooth rise when the filament forms | Threshold switching: a snap to the ON state at Vth in the amorphous state |
| Variation | Device-to-device and cycle-to-cycle, similar in both states | Noticeable, and worse in the amorphous states |
| Drift | Mild relaxation towards the middle in this model | Conductance drifts down as a power law of the time since the write, faster for amorphous states |
| Wear | The window closes after many cycles | Cells eventually stick in one state |
| Temperature | Heat speeds up filament relaxation, but heat is not the write mechanism | Heat is the write mechanism, so a hot chip speeds up drift and can erase data |
| Half-select (V/2) writing in a passive grid | Can work if V/2 stays below the switching threshold | Usually fails: V/2 of a RESET is hot enough to disturb neighbours, so each cell needs a transistor or selector |
| First use | An initial forming step creates the first filament | An initial crystallization of the as-deposited film |
| Availability | Needs a foundry with an RRAM oxide layer in the back-end | Needs a foundry with a chalcogenide layer in the back-end |
Both are small, dense, non-volatile cells whose conductance can serve as a weight. The model numbers on this page are illustrative and the real ranking of the two depends on the device stack.
Step 2 shows how a weight is written into a cell, and Step 3 is the crossbar simulator. Each difference above explains one of their controls, so here is a preview of what to look for.
Erase (RESET), SET pulses, program-and-verify and the pulse-count map exist in the ReRAM simulator too. In PCM the climb is one-directional: RESET is abrupt, so the write loop erases to the amorphous state first and then climbs one SET pulse at a time. Step 2 walks through it.
The σ slider and the write-noise model represent PCM’s imprecision (section 4 above). In the ReRAM simulator one σ applies about equally to every level. In PCM it is larger for the amorphous end of the range.
They represent the amorphous and crystalline states, as the high- and low-resistance states do for ReRAM. The PCM window is wider (about 100× against 20× here), but it is not symmetric: the low end is the noisy and drifting one.
Both cells have to be written to one of several conductance levels in between their two extremes. Because PCM levels are evenly spaced in dome size but not in conductance (section 2A), the simulator has to decide how to map weights onto them. ReRAM levels are closer to evenly spaced in this model.
This is a control the ReRAM simulator does not need, because ReRAM only relaxes slightly. After a PCM write, conductance falls as a power law, and the more amorphous the cell, the faster. The crossbar’s outputs will slide away from the ideal answer as time passes (section 4).
The read voltage is kept small (0.2 V by default) so that the cell stays well below its threshold voltage and below the temperature that would start to crystallize it, and the crossbar math holds (section 3).
The ReRAM crossbar can use a passive grid with the V/2 scheme. PCM cannot: a RESET at V puts V/2 across neighbours, which is hot enough to disturb them (section 2B). The array model needs a transistor or a selector in each cell.
The weights never move: they are the devices. That is where the energy saving over a digital multiply-accumulate comes from. But a PCM write is expensive (a RESET is tens of picojoules in this model), so the write cost is spread over how many times the weights are reused.
Because the read voltage is small. In that range the cell is far below its threshold voltage and the temperature stays well under the crystallization temperature, so the read does not change the phase and the I-V curve is close to linear. Each cell passes I = V·G with the G that was last written (allowing for drift).
PCM is changed by heat, and heat does not care about the sign of the current. A short, strong pulse melts the dome and freezes it as glass (RESET). A longer, gentler pulse of the same polarity crystallizes it (SET). In ReRAM the field moves ions, and the direction of the field decides whether the filament grows or dissolves, so the polarity has to flip.
The PCM cell. Its amorphous glass slowly relaxes into a more stable structure, so its conductance falls as a power law of the time since the write, by more in the high-resistance states. The ReRAM filament relaxes much less in this model (a drift toward the middle, not a power-law collapse). For weights, that means a PCM array needs drift compensation (a global rescale, or knowing the age of each cell), whereas the ReRAM one mostly does not.
They are still there, because the phase is a physical structure and non-volatile. They have drifted, though: the amorphous parts of each cell have relaxed, so conductance has fallen, by more in the high-resistance states than in the low-resistance ones. A long-lived system may need to refresh the weights or rescale the outputs to compensate.
RESET has to melt the dome and then freeze it before crystals can form, so it needs a lot of heat and a quick cool-down. SET has to hold the dome in the range where atoms are mobile, but not molten, long enough for crystal to grow from its edge. Crystal growth takes tens of nanoseconds, so a pulse that is too short does not finish the job, and a SET pulse that is too strong melts the dome and becomes a RESET.
Melting is abrupt. Once the pulse is above the melting point, the whole region over the heater turns amorphous at once, so RESET gives a big jump in G, not a small step. SET pulses, on the other hand, crystallize a bit at a time and are easy to count. The write loop therefore starts from the fully amorphous state and climbs one SET pulse at a time, reading back after each one.
They see V/2. With a RESET of about 3 V that is about 1.5 V, which is enough to heat them above the crystallization temperature, so the amorphous cells among them partly crystallize. The V/2 trick only works if V/2 is below what it takes to start heating, and a RESET needs far more than a ReRAM write. That is why PCM arrays use a transistor or a selector that blocks current below its own threshold. Try raising the amplitude in section 2 and watch the half-selected cells turn red.
A year later, almost exactly the same: their ages are 1 year and 1 year minus an hour, and drift is a power law in age, G ∝ t−ν, so the ratio is about 1. Right after the second write they differ a lot: the first cell is an hour (3600 s) old and has already fallen by a factor of about 3600−ν, which is ×0.56 for ν = 0.07, while the new one has not drifted yet. Drift is fast early and slow late, so compensating it in an array needs to know how old each cell is, or a global scaling that is good enough on average.
Now that a cell is a resistor you can program with heat, follow one weight from a number to a conductance: pick the cell, round to a level, erase to the amorphous state, then send SET pulses and read back until it is close enough. After that, the crossbar puts thousands of these cells in a grid.
Everything on this page is a teaching model, so its numbers are illustrative and not fitted to a real device. Start with the PCM review by Wong et al. (2010). The last two entries are the ReRAM sources to read against it. These sources are for the real physics and data.
The full, grouped list will be at the end of the crossbar simulator. Links can change, so searching the title and DOI always works. Citation details were checked against publisher or index records on 2 November 2026; volume and page numbers are given only where the record showed them.