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PCM Crossbar Simulator

A crossbar is a grid of phase-change cells. Each word line (a row) carries an input voltage, each bit line (a column) collects current, and a cell sits at every crossing with its stored conductance G.

Input voltages on the word lines produce bit-line currents that already equal the matrix product, Iⱼ = Σᵢ Vᵢ·Gᵢⱼ, so the multiply and the sum both happen inside the array. The array behaves like the PCM one, with two PCM differences you can switch on here: weights are written with the one-directional SET staircase from Step 2, and the stored conductances drift after the write.

This is a generic, textbook model of analog PCM compute-in-memory: a passive crossbar with differential conductance pairs, a quantized DAC and ADC, Gaussian device variation, wire IR drop, a pulse-and-verify write model and power-law drift. It is meant for learning and quick experiments, not as a model of any specific chip.

Path through this page: 1) Choose the array and encoding. 2) Set the inputs and weights. 3) Watch the crossbar compute, step by step. 4) Writing the weights and what it costs. 5) Age the array with Time since write and see the outputs slide away from the ideal answer, then try the global gain. 6) Efficiency against a digital multiply-accumulate.

Array size and cell encoding

Crossbar

A crossbar is a grid of PCM cells. Each word line (a row) carries an input voltage, each bit line (a column) collects current, and a cell sits at every crossing with its stored conductance G. Press Play to watch the five stages: write the weights, drive the rows, let each cell apply Ohm’s law, let each column sum its currents, then digitize the result. Use the controls beside the crossbar (below it on a narrow screen) to change the inputs, weights and device settings.

Word-line voltage Bit-line current Cell conductance (darker is higher G) Cell label
Negative weights: signed or unsigned, one cell or two? read when you reach negative weights

A PCM cell is a conductance G, and G can never be negative, so a current I = V·G can never be negative either. A weight is the number that scales an input, and weights are often negative as well as positive. Two separate design choices decide how the array copes, and you can set each one with the drop-downs above.

1. Weight sign: are negative weights needed?
Signed keeps them, so the output can go below zero. Unsigned gives up on them: a negative weight is stored as 0. That is fine when every weight is naturally positive (pixel intensities, counts, probabilities), and wrong when it is not.
2. Cells per weight: how is a signed weight stored?
G⁺/G⁻ pair uses two cells: one holds the positive part, one the negative part, and the column pair’s currents are subtracted. G⁺ only uses one cell. To keep negatives anyway it shifts the weight into 0 to 1 and subtracts a shared reference column that stands for zero.
Weight signCells per weightHow a weight is storedNegativesGmin leakageWeight stepCost
SignedPair (G⁺, G⁻)w > 0 goes in G⁺, w < 0 in G⁻, the other cell sits at Gmin. y = (I⁺ − I⁻) / (Vread·ΔG)KeptCancels (both cells leak equally)1/L2 cells per weight, 2 bit lines per output
SignedG⁺ onlyu = (w+1)/2 in 0 to 1, so w = 0 sits at the middle conductance. y = 2·(I − Iref) / (Vread·ΔG)KeptCancels (the reference column leaks too)2/L (twice as coarse)1 cell per weight, plus one shared reference column
UnsignedG⁺ onlyw ≥ 0 stored as is, w < 0 stored as 0. y = I / (Vread·ΔG)LostAdds an offset ≈ Σx·Gmin/ΔG to every output1/L1 cell per weight, no subtraction (simplest hardware)

L is the number of conductance levels minus one (set by “Weight levels”) and ΔG = Gmax − Gmin. The fourth combination, unsigned with a pair, is not offered: G⁻ would stay at Gmin and the second cell would buy nothing.

Why not always use the pair? It is the most accurate way to keep negatives, but it doubles the cells, the bit lines and the ADCs. If area or energy is tight, one cell per weight is attractive.
Why does the reference column halve the resolution? One cell has to cover weights from −1 to +1, so the same conductance range is spread over twice the span. Each level now means a change of 2/L in w instead of 1/L.
What does unsigned really cost? Negative weights turn into 0 and the leakage current of every cell piles up in the sum. The error is large when many weights are negative and small when none are.

Try it. (1) Press Randomize with Signed, pair, note y₁, then switch to Unsigned: negative weights turn red and y₁ moves. (2) Press “Make weights positive” and the unsigned result now differs from ideal only by the leakage offset. (3) Set σ = 0 and the ADC to 8 bits, then compare Signed, pair and Signed, G⁺ only: the same ideal answer, but the second is coarser when Weight levels is small. (4) Combine with Binary weighted cells to see the same three layouts at bit level.

Writing the weights into the array

Before any multiply, each weight has to be written as a conductance. The controller first RESETs the array to the amorphous, high-resistance state, then crystallizes each cell a little at a time with SET pulses, reading it back after every pulse and stopping when it is within tolerance of its target. A SET can only raise G, so if a pulse overshoots the cell is RESET and the climb starts again. The conductances this produces are the ones the crossbar uses, and they start to drift as soon as the write ends.

1.30 V
±2.0%
40
50 ns

Pulse sequence for one cell

Programming circuitry
Program-and-verify loop

Array write map

Each number is how many write pulses that cell needed. Darker means more. Cells aimed at the lowest conductance stay at their erased value and need none. That is why every G⁺/G⁻ pair has a 0: a positive weight is written into the G⁺ cell and a negative one into the G⁻ cell, and the other cell of the pair rests at Gmin. The counts come from this page’s illustrative write model with seeded random variation, so they show the shape of the effect, not the figures of a real device. The counts depend only on where each target sits between Gmin and Gmax, not on their µS values, so moving Gmin or Gmax changes the targets in µS but leaves these counts the same. Click a cell to inspect its pulse sequence. A red outline marks a cell that never reached its tolerance.

Result y = xᵀW

Trace one output

Efficiency versus digital multiply-accumulate

A conventional processor fetches every weight from memory and performs the M×N multiply-adds one batch at a time. The crossbar keeps the weights where they are and finishes all of them in a single read. The figures come from an illustrative energy and timing model, so adjust the assumptions to match a design you care about.

8
1.0 GHz
10 ns
1,000×
10 ns

References and further reading

This simulator is a teaching model. Its device behaviour (pulse response, variation, drift, energy and timing figures) is illustrative, not taken from a measured device. These papers describe the real systems it imitates. Links can change, so searching the title and DOI always works.

Phase-change memory and PCM weights supports the device settings, the write panels and drift

  1. Wong, H.-S. P., Raoux, S., Kim, S., Liang, J., Reifenberg, J. P., Rajendran, B., Asheghi, M. & Goodson, K. E. Phase change memory. Proceedings of the IEEE 98, 2201–2227 (2010). IEEE Xplore A review of the device physics, the materials, the scaling and the reliability of PCM, with a focus on memory use.
  2. Raoux, S. et al. Phase-change random access memory: a scalable technology. IBM Journal of Research and Development 52 (2008). IEEE Xplore Explains the mushroom cell, the SET and RESET operations and why the technology scales to small sizes.
  3. Wuttig, M. & Yamada, N. Phase-change materials for rewriteable data storage. Nature Materials 6, 824–832 (2007). doi:10.1038/nmat2009 Why some alloys switch between glass and crystal so quickly, and how the same materials are used in optical discs and in memory.
  4. Le Gallo, M. & Sebastian, A. An overview of phase-change memory device physics. Journal of Physics D: Applied Physics (2020). doi:10.1088/1361-6463/ab7794 A recent overview of threshold switching, crystallization, resistance drift and noise, written with in-memory computing in mind.
  5. Burr, G. W. et al. Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses) using phase-change memory as the synaptic weight element. IEEE Transactions on Electron Devices (2015). doi:10.1109/TED.2015.2439635 An early experiment that stored neural-network weights in a pair of PCM cells each, and what it took to tolerate their imperfections.
  6. Le Gallo, M. et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nature Electronics 6, 680–693 (2023). doi:10.1038/s41928-023-01010-1 A chip that does what the crossbar simulator in Step 3 models, built with PCM weights, and the drift and noise problems it had to handle.
  7. Wong, H.-S. P. et al. Metal–oxide RRAM. Proceedings of the IEEE 100, 1951–1970 (2012). doi:10.1109/JPROC.2012.2190369 A review of metal-oxide ReRAM: the switching mechanism, the materials and the electrical behaviour, with a focus on memory use.
  8. Waser, R. & Aono, M. Nanoionics-based resistive switching memories. Nature Materials 6, 833–840 (2007). doi:10.1038/nmat2023 A review of the physics behind resistive switching, where the movement of ions inside the material changes the cell’s resistance.

Crossbars, vector-matrix multiplication and in-memory computing supports the crossbar and the efficiency panel

  1. Hu, M. et al. Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), 1–6 (2016). doi:10.1145/2897937.2898010 An analog memristor-crossbar accelerator for matrix-vector multiplication, with a method for mapping matrix values onto device conductances. The abstract reports results with only 4-bit DACs and ADCs.
  2. Ielmini, D. & Wong, H.-S. P. In-memory computing with resistive switching devices. Nature Electronics 1, 333–343 (2018). doi:10.1038/s41928-018-0092-2 A review of in-memory computing with resistive devices, covering digital, analogue and stochastic schemes and the challenges that remain.
  3. Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. & Eleftheriou, E. Memory devices and applications for in-memory computing. Nature Nanotechnology 15, 529–544 (2020). doi:10.1038/s41565-020-0655-z · free version A broad overview of the memory devices used for in-memory computing and the computational primitives they enable, from signal processing to deep learning.

Writing the weights supports the Programming panel

  1. Alibart, F., Gao, L., Hoskins, B. D. & Strukov, D. B. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, 075201 (2012). doi:10.1088/0957-4484/23/7/075201 · arXiv:1110.1393 A feedback write algorithm that tuned the conductance of titanium-oxide devices to about 1% relative accuracy (roughly 7 bits) despite large variation in switching. The idea behind program-and-verify.

Splitting weights across several cells supports the Binary weighted cell encoding

  1. Shafiee, A. et al. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Computer Architecture News 44(3) (2016); presented at ISCA 2016. doi:10.1145/3007787.3001139 · author copy A crossbar accelerator that spreads each 16-bit weight over several memristor cells in the same row (2 bits per cell in the paper) and merges the columns with shifts and adds. The Binary weighted option is the 1-bit-per-cell extreme of the same idea.
Where to look things up

Equations, terms and settings, and the ReRAM comparison

Open the ReRAM crossbar next to this one and give both the same weights and σ. Then age the PCM array and watch the outputs move. The PCM reference page collects the equations with worked examples, a searchable glossary, symbols and units, and what every setting on this page does.