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ReRAM Crossbar Simulator

A crossbar is a grid of ReRAM cells. Each word line (a row) carries an input voltage, each bit line (a column) collects current, and a cell sits at every crossing with its stored conductance G.

Weights are stored as conductances in a resistive-RAM crossbar. Input voltages on the word lines produce bit-line currents that already equal the matrix product, Iⱼ = Σᵢ Vᵢ·Gᵢⱼ, so the multiply and the sum both happen inside the array.

This is a generic, textbook model of analog ReRAM compute-in-memory: a passive crossbar with differential conductance pairs, a quantized DAC and ADC, Gaussian device variation, wire IR drop and a pulse-and-verify model of how the weights are written. It is meant for learning and quick experiments, not as a novel architecture or a model of any specific chip.

Path through this page: 1) Warm-up: one cell, then two on a wire. 2) A 2×2 multiply, number by number. 3) The full crossbar. 4) How negative weights are stored. 5) Writing the weights and what it costs. 6) Efficiency against a digital multiply-accumulate. Extensions at the end are optional. Here a weight is simply a number that scales an input, and a vector-matrix multiply is a set of multiply-and-add sums done together.

Warm-up: one cell, then two cells on one wire start here

To read its stored value, a ReRAM cell acts like a resistor whose size you set when you program it. The only law you need is I = V × G: the current I equals the voltage V across the cell times its conductance G (the opposite of resistance). Think of water in a pipe: V is the pressure, G is how wide the pipe is, and I is how much water flows. Drag the sliders, then put a second cell on the same wire.

A crossbar column is this picture repeated: many cells share one bit line, each cell turns its row voltage into a current, and the wire adds them up. The conductance range of the sliders follows Gmin and Gmax in the Device and circuit panel.

Worked example: a real 2×2 vector multiply follow every number

Here the crossbar computes y = xᵀW for a 2-element input vector and a 2×2 weight matrix. The inputs from the vector x become voltages on the rows. The weights from the matrix W become conductances in the cells, two cells per weight (G⁺ and G⁻) because a conductance cannot be negative. Each column adds up its currents, and the result is compared with the exact answer. Inside each cell box the big number is its conductance and the small one is its current; tap a cell to see where they come from. Change any number, and use the Device and circuit settings beside the crossbar (DAC and weight bits, ADC bits, Gmin, Gmax, σ, wire resistance) to see where the differences come from. This example uses the analog multi-level layout. The Cell layout menu compares the default two-cell pair with two single-cell alternatives.

Input vector x (0 to 1)
Weight matrix W (−1 to 1)

Each box in the diagram is one ReRAM cell. The big number is its conductance G (in microsiemens, µS), and the small number is the current I (in microamps, µA) that flows through it. Both are labelled with their units. Tap any cell to see where its two numbers come from.

Predict first · 5 quick questions

Array size and cell encoding

Crossbar

A crossbar is a grid of ReRAM cells. Each word line (a row) carries an input voltage, each bit line (a column) collects current, and a cell sits at every crossing with its stored conductance G. Press Play to watch the five stages: write the weights, drive the rows, let each cell apply Ohm’s law, let each column sum its currents, then digitize the result. Use the controls beside the crossbar (below it on a narrow screen) to change the inputs, weights and device settings.

Word-line voltage Bit-line current Cell conductance (darker is higher G) Cell label
Negative weights: signed or unsigned, one cell or two? read when you reach negative weights

A ReRAM cell is a conductance G, and G can never be negative, so a current I = V·G can never be negative either. A weight is the number that scales an input, and weights are often negative as well as positive. Two separate design choices decide how the array copes, and you can set each one with the drop-downs above.

1. Weight sign: are negative weights needed?
Signed keeps them, so the output can go below zero. Unsigned gives up on them: a negative weight is stored as 0. That is fine when every weight is naturally positive (pixel intensities, counts, probabilities), and wrong when it is not.
2. Cells per weight: how is a signed weight stored?
G⁺/G⁻ pair uses two cells: one holds the positive part, one the negative part, and the column pair’s currents are subtracted. G⁺ only uses one cell. To keep negatives anyway it shifts the weight into 0 to 1 and subtracts a shared reference column that stands for zero.
Weight signCells per weightHow a weight is storedNegativesGmin leakageWeight stepCost
SignedPair (G⁺, G⁻)w > 0 goes in G⁺, w < 0 in G⁻, the other cell sits at Gmin. y = (I⁺ − I⁻) / (Vread·ΔG)KeptCancels (both cells leak equally)1/L2 cells per weight, 2 bit lines per output
SignedG⁺ onlyu = (w+1)/2 in 0 to 1, so w = 0 sits at the middle conductance. y = 2·(I − Iref) / (Vread·ΔG)KeptCancels (the reference column leaks too)2/L (twice as coarse)1 cell per weight, plus one shared reference column
UnsignedG⁺ onlyw ≥ 0 stored as is, w < 0 stored as 0. y = I / (Vread·ΔG)LostAdds an offset ≈ Σx·Gmin/ΔG to every output1/L1 cell per weight, no subtraction (simplest hardware)

L is the number of conductance levels minus one (set by “Weight levels”) and ΔG = Gmax − Gmin. The fourth combination, unsigned with a pair, is not offered: G⁻ would stay at Gmin and the second cell would buy nothing.

Why not always use the pair? It is the most accurate way to keep negatives, but it doubles the cells, the bit lines and the ADCs. If area or energy is tight, one cell per weight is attractive.
Why does the reference column halve the resolution? One cell has to cover weights from −1 to +1, so the same conductance range is spread over twice the span. Each level now means a change of 2/L in w instead of 1/L.
What does unsigned really cost? Negative weights turn into 0 and the leakage current of every cell piles up in the sum. The error is large when many weights are negative and small when none are.

Try it. (1) Press Randomize with Signed, pair, note y₁, then switch to Unsigned: negative weights turn red and y₁ moves. (2) Press “Make weights positive” and the unsigned result now differs from ideal only by the leakage offset. (3) Set σ = 0 and the ADC to 8 bits, then compare Signed, pair and Signed, G⁺ only: the same ideal answer, but the second is coarser when Weight levels is small. (4) Combine with Binary weighted cells to see the same three layouts at bit level.

Writing the weights into the array

Before any multiply, each weight has to be written as a conductance. The controller first erases the array to the high-resistance state, then nudges each cell with SET pulses (raise G) and RESET pulses (lower G), reading it back after every pulse and stopping when it is within tolerance of its target. The conductances this produces are the ones the crossbar above computes with. The device model is a simple illustrative one, so adjust it to explore the trade-offs.

1.00 V
0.10 V
±2.0%
30
50 ns
50 µA

Pulse sequence for one cell

Programming circuitry
Program-and-verify loop

Array write map

Each number is how many write pulses that cell needed. Darker means more. Cells aimed at the lowest conductance stay at their erased value and need none. That is why every G⁺/G⁻ pair has a 0: a positive weight is written into the G⁺ cell and a negative one into the G⁻ cell, and the other cell of the pair rests at Gmin. The counts come from this page’s illustrative write model with seeded random variation, so they show the shape of the effect, not the figures of a real device. The counts depend only on where each target sits between Gmin and Gmax, not on their µS values, so moving Gmin or Gmax changes the targets in µS but leaves these counts the same. Click a cell to inspect its pulse sequence. A red outline marks a cell that never reached its tolerance.

Result y = xᵀW

Trace one output

Efficiency versus digital multiply-accumulate

A conventional processor fetches every weight from memory and performs the M×N multiply-adds one batch at a time. The crossbar keeps the weights where they are and finishes all of them in a single read. The figures come from an illustrative energy and timing model, so adjust the assumptions to match a design you care about.

8
1.0 GHz
10 ns
1,000×
10 ns

Extensions optional, after the main path

Example 1 uses the crossbar as a tiny pattern matcher. Example 2 repeats Step 2 on the matrix loaded in the simulator. Example 3 shows why one crossbar is not always enough.

Example 1: which side of the picture is lit? tiny example

Pick a 2×2 picture (4 pixels) or a 3×3 patch (9 pixels). The array stores four templates: Left, Right, Top and Bottom. Each template is a column of weights: +1 for “I want this pixel lit”, −1 for “I want it dark”, and 0 for “I don’t care” (3×3 only). The picture goes in as voltages, every cell adds its current to its bit line, and the template that overlaps the picture most collects the most current. In the 3×3 case the templates are edge-detecting kernels like those used in image processing, so this is one step of a convolution. It is a one-layer neural network (a weighted sum per template, then pick the biggest), computed in a single read.

1. Draw the picture (tap pixels)
Or try a preset
2. Templates (weights) and 3. what each bit line adds up

Example 2: how does a weight get written into a cell? step by step

A ReRAM cell can’t be set to an exact value with one pulse, because every device responds a little differently. So each weight is written with a short loop: pulse, read the cell back, compare with the target, and repeat until it is close enough. Tap any number in the matrix (it is the matrix currently in the simulator, so load the example above to see its templates) and step through how it is stored in a pair of cells. SET and RESET are opposite-polarity pulses applied across the cell; Step 1 shows what each does to the filament and where the pulse is injected.

1. Pick a weight
10.0%

This is the same write model as the Programming panel further down (with Write method set to Program-and-verify), so the same cell gets the same pulses there. Different cells need different numbers of pulses because each device responds a little differently: raise the variation σ and tap a few weights to see it. The Programming panel also shows the circuit, the pulse waveform and the cost of writing the whole array.

Example 3: why XOR needs two crossbars

XOR is 1 when exactly one of the two inputs is on. One crossbar can only draw a single straight line through the four cases, and no line separates XOR’s 0s from its 1s. With two crossbars and a comparator in between it works: A asks “is any input on?” (h₁) and “are both on?” (h₂), and B answers “any, but not both”.

Inputs (tap to flip)
bias = 1 (always on)

Experiment: edit the weights, add noise
10.0%
0 Ω

Weights go from −1 to 1. Push σ toward 20 to 25% and press Resample a few times: a ✗ appears when noise on one cell pushes a sum across 0. The other device settings come from the Device and circuit panel beside the crossbar, and weights are written ideally with no programming model.

References and further reading

This simulator is a teaching model. Its device behaviour (pulse response, variation, energy and timing figures) is illustrative and not fitted to any particular device, so use the sources below for real data. They are grouped by the part of the page they support. Citation details were checked against publisher or index records on 1 November 2026, and links can change, so searching the title and DOI always works.

Memristors and ReRAM devices supports the device settings and the write panels

  1. Chua, L. O. Memristor — the missing circuit element. IEEE Transactions on Circuit Theory 18, 507–519 (1971). Proposes the memristor as a fourth basic circuit element, in effect a resistor with memory.
  2. Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found. Nature 453, 80–83 (2008). doi:10.1038/nature06932 Reports a nanoscale titanium-oxide device that behaves like a memristor. Widely cited as the paper that renewed interest in the idea.
  3. Waser, R. & Aono, M. Nanoionics-based resistive switching memories. Nature Materials 6, 833–840 (2007). doi:10.1038/nmat2023 A review of the physics behind resistive switching, where the movement of ions inside the material changes the cell’s resistance.
  4. Wong, H.-S. P. et al. Metal–oxide RRAM. Proceedings of the IEEE 100, 1951–1970 (2012). doi:10.1109/JPROC.2012.2190369 A review of metal-oxide ReRAM: the switching mechanism, the materials and the electrical behaviour, with a focus on memory use.
  5. Govoreanu, B. et al. 10×10 nm² Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. IEEE International Electron Devices Meeting (IEDM), 31.6.1–31.6.4 (2011). imec repository A hafnium-oxide ReRAM cell smaller than 10 nm × 10 nm in a crossbar, reported with fast low-voltage switching and high endurance.
  6. Ielmini, D. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling. Semiconductor Science and Technology 31, 063002 (2016). doi:10.1088/0268-1242/31/6/063002 A review of how oxide ReRAM switches, how reliable it is, and how it scales.

Crossbars, vector-matrix multiplication and in-memory computing supports the crossbar, Example 1 and the efficiency panel

  1. Hu, M. et al. Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), 1–6 (2016). doi:10.1145/2897937.2898010 An analog memristor-crossbar accelerator for matrix-vector multiplication, with a method for mapping matrix values onto device conductances. The abstract reports results with only 4-bit DACs and ADCs.
  2. Ielmini, D. & Wong, H.-S. P. In-memory computing with resistive switching devices. Nature Electronics 1, 333–343 (2018). doi:10.1038/s41928-018-0092-2 A review of in-memory computing with resistive devices, covering digital, analogue and stochastic schemes and the challenges that remain.
  3. Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. & Eleftheriou, E. Memory devices and applications for in-memory computing. Nature Nanotechnology 15, 529–544 (2020). doi:10.1038/s41565-020-0655-z · free version A broad overview of the memory devices used for in-memory computing and the computational primitives they enable, from signal processing to deep learning.

Writing the weights supports Example 2 and the Programming panel

  1. Alibart, F., Gao, L., Hoskins, B. D. & Strukov, D. B. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, 075201 (2012). doi:10.1088/0957-4484/23/7/075201 · arXiv:1110.1393 A feedback write algorithm that tuned the conductance of titanium-oxide devices to about 1% relative accuracy (roughly 7 bits) despite large variation in switching. The idea behind program-and-verify.

Neural networks on ReRAM hardware supports the examples, including XOR (Example 3)

  1. Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015). doi:10.1038/nature14441 Experimental memristor crossbars with variability low enough to run a small network, a single-layer perceptron. Such a network can only classify linearly separable patterns, the limit the XOR panel demonstrates.
  2. Wan, W. et al. A compute-in-memory chip based on resistive random-access memory. Nature 608, 504–512 (2022). doi:10.1038/s41586-022-04992-8 · open access NeuRRAM, a fabricated ReRAM compute-in-memory chip with 48 cores. A good look at what a complete chip around a crossbar involves.

ReRAM in silicon with SKY130 tools and announcements, not peer-reviewed papers

  1. SkyWater PDK, sky130_fd_pr_reram: primitives for ReRAM on SKY130 provided by SkyWater. foss-eda-tools.googlesource.com (mirrored at github.com/google/skywater-pdk-libs-sky130_fd_pr_reram) The open ReRAM cell with layout, SPICE and Verilog-AMS views, plus test designs. Read its documentation for the model’s actual behaviour and limits before comparing it with this simulator.
  2. open_pdks, the build system that produces the sky130A (standard) and sky130B (with the ReRAM option) kits. foss-eda-tools.googlesource.com Explains how the two variants are built and which one a shuttle service uses.
  3. Weebit Nano ReRAM IP now available in SkyWater Technology’s S130 process. Press release, 7 March 2023. skywatertechnology.com Announces a commercial ReRAM memory module in SkyWater’s 130 nm process. It is a finished memory block, separate from the open cell above.
  4. Cadence and SkyWater detail next open multi-project wafer shuttle program. Electronics-Lab. electronics-lab.com News article on a SKY130 shuttle offering a standard process and one with embedded ReRAM. The submission window it describes has closed, so check the current shuttle schedule.

Splitting weights across several cells supports the Binary weighted cell encoding

  1. Shafiee, A. et al. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Computer Architecture News 44(3) (2016); presented at ISCA 2016. doi:10.1145/3007787.3001139 · author copy A crossbar accelerator that spreads each 16-bit weight over several memristor cells in the same row (2 bits per cell in the paper) and merges the columns with shifts and adds. The Binary weighted option is the 1-bit-per-cell extreme of the same idea.
Where to look things up

Equations, terms and settings

The reference page collects the equations with worked examples, a searchable glossary, symbols and units, and what every setting on this page does. To see how a single weight reaches a cell, go back to Step 2.