Reference · Step 1: ReRAM basics · Step 2: writing a weight · Step 3: crossbar simulator · ReRAM home · Compare with PCM

ReRAM reference

The equations, terms, symbols and settings used across the three steps, in one place. Keep it open next to the simulator, or use it to look something up when a word is new.

Learning path

Three short lessons, each building on the one before. If you are new to this, go in order.

Step 1

ReRAM vs an ordinary resistor

A cell is a resistor you can reprogram with pulses, and it keeps its value without power. You will SET, RESET and read one.

Step 2

How a weight gets written

From a number to a conductance: choose the cell, round to a level, erase, then pulse and read back until it is close enough.

Step 3

The crossbar simulator

Put cells in a grid. Voltages in, Ohm's law in every cell, currents added on the wires: a matrix multiply in one read.

The signal chain in one line

Everything in the simulator sits somewhere on this path. The middle is analog. The two ends are converters to and from the digital world.

digital
Input x
0 to 1
A number from the model or the previous layer.
converter
DAC
V = x × V_read
Rounds the input and makes a voltage.
analog
Word lines
V_1 … V_M
One voltage per row, all applied at once.
analog
Cells
I = V × G
Each cell stores a weight as G and multiplies.
analog
Bit lines
I = Σ V × G
The currents of a column add on the wire.
analog
Subtract
I⁺ − I⁻
The pair gives a signed result.
converter
ADC
code → y
Turns the current into an integer, then a number.

Key equations

Each one has a worked example with the simulator's default numbers and a pointer to where you can see it. Equations 8 to 10 describe this teaching model, not a measured device.

1. Ohm's law, one cell

I = V × G      (G = 1 / R)

The current through a cell is the voltage across it times its conductance. This is the multiplication.

Example. 0.2 V × 50 µS = 10 µA (the same cell is 20 kΩ).

Used in: Step 1 (read a cell). Step 2 trace table.

2. Kirchhoff's current law, one bit line

I_j = Σ_i  V_i × G_ij

All cells on a bit line feed one wire, and the currents simply add. This is the accumulation.

Example. 0.10 V × 60 µS + 0.20 V × 30 µS = 6 + 6 = 12 µA.

Used in: Step 2, walkthrough step 4 (Sum columns).

3. Input to voltage (DAC)

V_i = x_i × V_read

An input between 0 and 1 is rounded to one of 2^b − 1 steps and turned into a word-line voltage no larger than the read voltage.

Example. x = 0.5 and V_read = 0.2 V give 0.10 V. With a 4-bit DAC the steps are 1/15 apart.

Used in: Step 2, Input DAC slider.

4. Weight to conductance

level = round(|w| × (L − 1))
G = Gmin + level / (L − 1) × (Gmax − Gmin)
L = 2^bits

The weight magnitude is rounded to one of L levels and mapped linearly onto the window between Gmin and Gmax. The sign picks the G⁺ or G⁻ cell.

Example. |w| = 0.62 with 3 bits: level = round(4.34) = 4, so G = 5 + 4/7 × 95 = 59.3 µS.

Used in: Step 3, step 3 (Round to a level).

5. Differential read-out

y = (I⁺ − I⁻) / (V_read × (Gmax − Gmin))

Subtract the two bit-line currents of a pair and divide by the scale factor to turn current back into a number. Gmin is in both cells and cancels.

Example. x = 0.5, G⁺ = 59.3 µS, G⁻ = 5 µS: I⁺ = 5.93 µA, I⁻ = 0.50 µA, so y = 5.43 / 19 = 0.286 (the ideal for the rounded weight is 0.5 × 0.571 = 0.286).

Used in: Step 2, Result table. Step 3, step 6.

5b. Two other ways to store the sign

G⁺ only + reference column:
  level = round((w + 1)/2 × L),   G = Gmin + level/L × (Gmax − Gmin)
  G_ref = Gmin + (Gmax − Gmin)/2   (every row of the reference column)
  y = 2 × (I − I_ref) / (V_read × (Gmax − Gmin))

Unsigned, negatives clipped:
  level = round(max(w, 0) × L),   G = Gmin + level/L × (Gmax − Gmin)
  y = I / (V_read × (Gmax − Gmin))

The differential pair spends two cells per weight. These two spend one. With a reference column the weight is shifted into 0 to 1 and the middle conductance stands for zero, so negatives work and the Gmin leakage cancels, but one set of levels covers both signs, so each step in w is twice as coarse. With no subtraction at all, negative weights are lost and the leakage of every cell stays in the sum.

Example. x = 0.5 (V = 0.1 V), w = 0.6, L = 15, Gmin = 5 µS, Gmax = 100 µS. Reference column: level 12, G = 81 µS, I = 8.1 µA, I_ref = 0.1 × 52.5 = 5.25 µA, so y = 2 × 2.85 / 19 = 0.300, which is exactly x × w. Unsigned: level 9, G = 62 µS, I = 6.2 µA, so y = 6.2 / 19 = 0.326. The extra 0.026 is the leakage x × Gmin/(Gmax − Gmin).

Used in: Step 3, Weight sign setting and the worked example.

6. Output ADC

step = R / (2^(b−1) − 1)
R = rows × ADC range

The converter has 2^(b−1) − 1 steps on each side of zero between −R and +R. Smaller R gives finer steps, but any output larger than R is clipped. (Default analog layout.)

Example. 4 rows, 100% range, 8 bits: R = 4, step = 4 / 127 = 0.031.

Used in: Step 2, Output ADC and ADC range sliders.

7. The write loop

V_n = V_0 + n × ΔV
stop when  |G − G_target| ≤ tol × (Gmax − Gmin)

Each pulse in the same direction is a little stronger than the last. After every pulse the cell is read, and the loop ends when it is close enough or the pulse limit is reached. If a pulse overshoots, the loop switches to the other polarity and restarts from V_0.

Example. V_0 = 1.0 V and ΔV = 0.10 V give 1.0, 1.1, 1.2 V. A 2% tolerance on a 95 µS window is ± 1.9 µS.

Used in: Step 3, step 5. Step 2, write panel.

8. How a pulse moves the cell (teaching model)

drive = clamp((V − 0.8) / (2.4 − 0.8), 0, 1)
SET:    G ← G + 0.45 × drive × (Gmax − G) × f
RESET:  G ← G − 0.45 × drive × (G − Gmin) × f

Pulses below 0.8 V do nothing. Stronger pulses move G a larger fraction of the remaining distance toward Gmax (SET) or Gmin (RESET). f is a random factor near 1 whose spread is set by σ: part of it is fixed per cell and part changes each pulse. This is an illustrative rule, not a measured device equation.

Example. G = 5 µS and a 1.0 V SET: drive = 0.125, so G rises by about 0.45 × 0.125 × 95 = 5.3 µS (to about 10.3 µS when f = 1).

Used in: Step 1 and Step 3, step 5.

9. Time and energy of a write (teaching model)

SET pulse:    E = V × I_cc × t_p
RESET pulse:  E = V² × G × t_p
Verify read:  E = V_read² × G × t_read + E_ADC
(+ 0.5 pJ driver energy per pulse)

Units work out as volts × µA × ns = femtojoules. Time is t_p per pulse plus (t_read + t_ADC) per verify read. Cells in one row are written in parallel, so a row takes as long as its slowest cell.

Example. One 1.0 V SET pulse with I_cc = 50 µA and t_p = 50 ns: 1.0 × 50 × 50 = 2500 fJ = 2.5 pJ, plus 0.5 pJ, so 3.0 pJ.

Used in: Step 3, step 6. Step 2, write panel.

10. Compute energy and break-even reuse (teaching model)

E_crossbar = Σ V × I × t_read
           + inputs × E_DAC + columns × E_ADC
E_digital  = (M × N) × (E_MAC + E_fetch)
break-even = E_write / (E_digital − E_crossbar)

The crossbar pays once to write its weights and then a small amount per product. The digital processor pays to fetch every weight on every product. The crossbar only wins on energy after enough products reuse the same weights. The constants in the efficiency panel are ballpark values you can edit.

Example. If writing the weights costs 1,400 pJ and each product saves 15 pJ, the break-even is about 93 products.

Used in: Step 2, efficiency panel.

11. IR drop

solved numerically (Gauss-Seidel)

There is no short formula. Every wire segment has a resistance R_w, and the simulator solves the whole network of cells and wires. Cells far from the drivers see less than the intended voltage, so their currents come out lower than the ideal. Larger conductances draw more current, so they make the drop worse.

Example. With 200 Ω segments the output error in the default example grows from 0.070 (Gmax = 40 µS) to 0.164 (Gmax = 200 µS).

Used in: Step 2, Wire R slider.

Glossary

Type to filter the 38 terms by name or by anything in the definition.

1T1R: One access transistor in series with each cell. The transistor selects the cell to write and limits the current during SET. This simulator draws a passive crossbar with no transistors and has a separate SET compliance setting for the current limit.
ADC (analog-to-digital converter): Turns a bit-line current into an integer code. More bits give finer output steps. In the efficiency model each extra bit doubles the ADC's energy.
Bit line (BL): The wire that runs down a column and collects the currents of every cell in it. Its total current is the sum of V × G over the column.
Bit slicing (binary weighted encoding): Storing each bit of a weight in its own pair of two-state cells and combining the bit planes with shifts and adds in digital logic. It uses more cells and more ADC conversions, but each cell only needs two well-separated states. The Cell encoding menu in Step 2 offers it.
Block erase: A single strong RESET pulse applied to a block of cells so that all of them start from the high-resistance state before writing.
Compute-in-memory (in-memory computing): Doing arithmetic inside the memory array where the data is stored, instead of moving the data to a separate processor.
Conductance (G): How easily a cell passes current. G = 1 / R, measured in siemens (S). The cells here sit between 5 and 100 µS, which is 200 kΩ down to 10 kΩ. Conductances on a shared wire simply add, which is why weights are stored as conductance and not as resistance.
Conductive filament: A thin channel of oxygen vacancies through the metal-oxide layer. A SET pulse builds or widens it and a RESET pulse dissolves part of it. Its size sets the cell's conductance.
Crossbar: A grid of word lines crossing bit lines, with one memory cell at every crossing.
Cycle-to-cycle variation: The same cell responds a little differently to the same pulse each time it is written.
DAC (digital-to-analog converter): Turns an input number into a voltage on a word line. The simulator rounds inputs to 2^b − 1 steps.
Device-to-device variation: Different cells respond differently to the same pulse, because no two filaments form identically. The σ slider sets how large the spread is.
Differential pair (G⁺ / G⁻): Two cells that together store one signed weight. The positive part goes in G⁺, the negative part in G⁻, and the read-out subtracts the two currents.
Reference column: One extra column of cells, all at the middle conductance Gmid, shared by every output. Its current is subtracted from each output, so a single cell per weight can still stand for a negative weight.
Unsigned encoding (negatives clipped): One cell per weight and no subtraction. A cell cannot be negative, so negative weights are stored as 0, and the Gmin leakage of every cell adds a small offset to each output.
Drift (retention loss): The stored conductance slowly wanders over time, even with the power off. Step 1 has a time slider that shows it.
Endurance: How many SET and RESET cycles a cell survives before its window shrinks or it stops switching. Step 1 has a write-cycles slider that shows it.
Forming: A one-time, higher-voltage step that creates the first filament in many oxide ReRAM cells. This teaching model leaves it out.
High-resistance state (HRS) and low-resistance state (LRS): The two extremes of a cell. HRS is the lowest conductance (Gmin) and LRS is the highest (Gmax). Between them the cell can hold intermediate analog levels.
IR drop: Voltage lost along the resistance of the wires. Cells far from the drivers see less voltage, so their currents are lower than the ideal. The Wire R slider controls it and the simulator solves for it.
HfOx (hafnium oxide): A common oxide for ReRAM. Hafnium dioxide (HfO₂) is also used as a thin gate insulator in advanced CMOS, so it fits standard chip processes. The x means the oxygen content is not fixed. Switching moves oxygen ions and builds a filament of oxygen vacancies. This simulator is generic and does not model HfOx specifically.
ISPP (incremental step pulse programming): A write scheme where each new pulse is a little higher in amplitude than the last (V₀ + n × ΔV), with a read between pulses. The default write method in the simulator.
Kirchhoff's current law: The currents flowing into a point add up to the currents flowing out. It is why all the cell currents on one bit line sum into a single current.
Level (conductance level): One of the 2^b discrete conductance values a cell is aimed at. Level k of L − 1 steps sits at Gmin + k / (L − 1) × (Gmax − Gmin).
Matrix-vector multiplication (MVM): y = xᵀW: every output is the dot product of the input vector with one column of weights. It is the main operation inside neural-network layers.
Memristor: A resistor whose value depends on the history of the current through it. Leon Chua proposed the idea in 1971, and ReRAM cells are often described as memristive devices. The memristor is an ideal circuit element. Real ReRAM cells have a switching threshold, variation, drift and wear that the ideal model leaves out.
Multiply-accumulate (MAC): One multiplication added to a running total. A matrix-vector product is many MACs.
Neural network (NN): A model built from layers. Each layer computes weighted sums of its inputs and then applies a simple nonlinear function. The weights are numbers learned during training. These lessons only need the weighted sum, which a crossbar computes in one read.
Non-volatile: Keeps its stored state with the power off.
Ohm's law: V = I × R, or equivalently I = V × G. It is the multiplication step in the crossbar.
On/off ratio (window): Gmax / Gmin. With the defaults, 100 / 5 = 20. A wider window leaves more room between levels.
Open-loop write: Applying a fixed train of pulses without reading the cell back. It is cheap, but device variation lands directly in the stored weight.
Oxygen vacancy: A missing oxygen atom in the oxide. Vacancies conduct better than the surrounding oxide, so a chain of them through the film is the conductive filament. A SET pulse moves oxygen ions and lines the vacancies up, and a RESET pulse refills them.
Program-and-verify (write-verify): Writing in a loop: pulse, read back, compare with the target, and repeat until the cell is within tolerance or the pulses run out.
Quantization: Rounding to one of a limited set of values: inputs by the DAC, weights to conductance levels, outputs by the ADC.
Read disturb: A read at too high a voltage nudges the stored state. The read voltage is kept low to avoid it. Step 1 shows it.
ReRAM (resistive RAM, RRAM): Resistive random-access memory. A cell stores a value as its resistance, set by a filament in a thin oxide, and keeps it with the power off. Any cell can be reached by its address. It can be used as a memory bit (two states) or as a neural-network weight (many levels).
RESET: A pulse that lowers a cell's conductance by dissolving part of the filament. In this model the block erase is a strong RESET.
SET: A pulse that raises a cell's conductance by building or widening the filament.
Sneak path: In a passive crossbar, current that finds a route through other cells instead of the selected one, which corrupts reads and writes. Transistors (1T1R) or selector devices suppress it. This simulator does not model sneak paths.
Tolerance: How close to the target counts as done in a verify loop, set as a percent of the Gmax − Gmin window.
Von Neumann bottleneck: The time and energy spent moving data between a separate memory and processor. Computing in the array avoids moving the weights.
Weight: A number the model learned. Here it runs from −1 to +1 and is stored as conductance in one or two cells.
Word line (WL): The wire that runs along a row and carries one input voltage to every cell in that row.

Symbols and units

The defaults are the values the simulator starts with.

Symbol	Meaning	Unit	Default or rule
x_i	Input value for row i	0 to 1	set with the input sliders
V_i	Voltage on word line i	V	x_i × V_read
V_read	Read voltage	V	0.2
w_ij	Weight in row i, output j	−1 to +1	set in the weight matrix
G_ij	Conductance of one cell	µS	Gmin to Gmax
Gmin, Gmax	Conductance of the high- and low-resistance states	µS	5 and 100
ΔG	The window, Gmax − Gmin	µS	95
b, L	Bits per weight and number of levels, L = 2^b	bits, count	4 bits, 16 levels
M, N	Rows (inputs) and outputs. There are 2N bit lines	count	4 and 4
I_j	Current on bit line j	µA	Σ V_i × G_ij
y_j	Output j after read-out and ADC	none	ideal: Σ x_i × w_ij
σ	Device variation	%	10
R_w	Wire resistance per segment	Ω	0
V_0, ΔV	First write amplitude and step per pulse	V	1.0 and 0.10
tol	Verify tolerance as a share of ΔG	%	2
t_p	Write pulse width	ns	50
I_cc	SET compliance (current limit)	µA	50
t_read, t_ADC	Read pulse and ADC conversion time	ns	10 and 10

1 µS = 10⁻⁶ siemens, which is a resistance of 1 MΩ. 100 µS is 10 kΩ. A voltage in volts times a conductance in µS gives a current in µA. A voltage times a current in µA times a time in ns gives energy in fJ (1,000 fJ = 1 pJ).

What each setting does

Each row says what happens when you raise the setting. The numbers are the RMS output error (or the write cost) measured on the simulator's default 4 × 4 example with 10% variation and program-and-verify writing, changing one setting at a time. They are a guide to the direction and size of each effect, and will shift if you change other settings or the simulator is updated.

Array and signal chain

Control	What it is	Raise it, and what happens	Used in
Array size	Rows and outputs.	More rows add more products per read, but also longer wires (more IR drop) and more cells to write.	Step 2
Cell encoding	Analog multi-level (one cell holds any of 2^bits levels) or binary weighted (one 1-bit cell per weight bit, planes combined by shift and add).	Binary weighted uses as many bit planes as the Weight levels setting, so more cells and more ADC conversions, but each cell only needs two well-separated states and tolerates far more variation.	Step 3
Weight sign and cells per weight	Two settings. Weight sign: Signed keeps negative weights, Unsigned stores them as 0. Cells per weight: a G⁺/G⁻ pair (two cells) or G⁺ only (one cell, with a shared reference column when signed).	The pair uses two cells per weight. The reference column and the unsigned layout use about half as many cells. The reference column keeps negatives but makes each step in w twice as coarse. Unsigned loses negatives and adds a Gmin offset to every output.	Step 3
Input DAC (1 to 8 bits)	Resolution of the input voltages.	Finer inputs and lower error: RMS error 0.090, 0.046 and 0.038 at 2, 4 and 8 bits in the default example. DAC energy doubles with each bit.	Step 2
Weight levels (1 to 8 bits)	How many conductance levels a weight can take.	Finer weights and lower error: 0.122, 0.046 and 0.032 at 2, 4 and 8 bits. The levels also sit closer together, so they are harder to hit.	Steps 2, 3
Output ADC (3 to 12 bits)	Resolution of the converter on each bit-line pair.	Lower error: 0.125, 0.046 and 0.039 at 4, 8 and 12 bits. ADC energy doubles with each bit.	Step 2
ADC range (20 to 100%)	Full scale as a share of the number of rows.	Too small clips large outputs (error 0.288 at 20%). Too large wastes resolution (0.046 at 100% against 0.041 at 50%). Pick a range just above the largest expected output.	Step 2
Read voltage (0.05 to 0.3 V)	Voltage that a full-scale input puts on a word line.	Scales every current and the array energy. It does not change accuracy in this model. On real devices a high read voltage can disturb the cell (Step 1).	Steps 1, 2
Gmin and Gmax	The two ends of the conductance window.	Alone they scale the currents and the energy but not the accuracy. Raising Gmax makes IR drop worse (error 0.070, 0.101 and 0.164 at 40, 100 and 200 µS with 200 Ω wires). Raising Gmin narrows the window, so variation matters more (0.088, 0.096 and 0.146 at 1, 5 and 20 µS with ideal writes).	Steps 1, 2
Variation σ (0 to 25%)	Spread in how cells respond.	With ideal writes it goes straight into the weights (error 0.019, 0.096 and 0.263 at 0, 10 and 25%). Open-loop writes suffer too. Program-and-verify cancels most of it, so what is left is mainly the tolerance.	Steps 1, 2, 3
Wire R per segment (0 to 300 Ω)	Resistance of each wire segment.	More IR drop and more error: 0.046, 0.056 and 0.146 at 0, 100 and 300 Ω.	Step 2

Writing the weights

Control	What it is	Raise it, and what happens	Used in
Write method	Program-and-verify, open loop, or ideal.	Verify reads back after every pulse. Open loop replays a fixed pulse train, which is cheaper but leaves the variation in. Ideal skips programming and adds only Gaussian variation.	Steps 2, 3
Start amplitude (0.8 to 2 V)	Amplitude of the first pulse.	Too low wastes pulses, since pulses near 0.8 V barely move the cell (151 pulses at 0.8 V against 105 at 1.0 V). Too high lands coarse and costs more energy (2.0 V: 1,847 pJ against 1,401 pJ, and one cell out of tolerance).	Steps 2, 3
Step ΔV (0.02 to 0.3 V)	How much each pulse is stronger than the last.	Smaller steps need more pulses (159 at 0.02 V against 95 at 0.3 V) and give a more gradual approach.	Steps 2, 3
Verify tolerance (0.5 to 10%)	How close counts as done.	Looser is cheaper and less accurate: 178, 105 and 79 pulses and error 0.020, 0.046 and 0.088 at 0.5, 2 and 10%.	Steps 2, 3
Max pulses per cell (1 to 60)	Pulse limit before the loop gives up.	Too low and cells stop before they arrive (error 0.619, 0.210 and 0.046 at 2, 6 and 30).	Steps 2, 3
Pulse width (10 to 500 ns)	Duration of each write pulse.	Longer pulses cost more time and energy (1.3 µs and 617 pJ at 10 ns, 21.9 µs and 10.2 nJ at 500 ns). Accuracy is unchanged in this model.	Step 2
SET compliance (10 to 200 µA)	Current limit during SET.	In this model it only sets the energy of each SET pulse (1,154 pJ at 10 µA, 2,325 pJ at 200 µA). On real devices it also strongly affects the filament.	Step 2
Write order	A row at a time, or one cell at a time.	Changes write time only (3.0 µs against 8.0 µs for the 4 × 8 default array).	Step 2
Block erase first	Counts the cost of the erase.	Switching it off removes about 650 pJ from the default array's write energy (745 pJ against 1,401 pJ) but the cells then start from old data.	Steps 2, 3

Efficiency panel

Control	What it is	Raise it, and what happens	Used in
Digital weight source	Where the processor fetches weights from.	SRAM costs about 1.3 pJ per weight in the model and DRAM about 160 pJ. DRAM makes the digital side far more expensive, so the crossbar wins sooner.	Step 2
MAC lanes and clock	How many multiply-adds the digital side does at once, and how fast.	More lanes and a faster clock cut the digital latency. The crossbar's latency does not depend on them.	Step 2
ReRAM read pulse and ADC conversion	Time to read the array and to convert the result.	Together they set the crossbar's latency for one product. They do not depend on array size.	Step 2
Weight reuse	How many products reuse one set of written weights.	Spreads the one-time write cost over more products. The table shows the break-even.	Step 2

Common questions

Why store a weight as conductance and not resistance?

Because currents on a shared wire add in terms of conductance: I = V × (G₁ + G₂ + ...). Resistances in parallel combine through reciprocals, which does not give a sum. With conductance, the wire does the accumulation for free.

Why does a weight need two cells?

A conductance cannot be negative. One cell holds the positive part and one holds the negative part, and the read-out subtracts them. Step 3 walks through it.

Does reading a cell erase or change the weight?

Not at a small read voltage. The read stays inside the range where the cell acts like a plain resistor. A read at a high voltage can nudge the state, which is called read disturb (Step 1).

Is the crossbar analog or digital?

The array itself is analog: voltages go in, currents add, and a current comes out. The DACs and ADCs at the edges are the interface to the digital system around it.

If ReRAM is so efficient, why does not every chip use it?

Writing is slow and costly, cells vary and drift, endurance is limited, large arrays suffer IR drop and sneak paths, and the converters take energy and area. It suits cases where the same weights are read many times, such as running a trained network. The efficiency panel in Step 2 lets you see where the advantage appears and where it does not.

Why verify after each pulse?

The same pulse moves different cells by different amounts. Reading back lets the controller stop each cell near its target. In Step 3, switch to open loop and press Try a different cell to see the spread.

Is this simulator a model of a real chip?

No. It is a generic teaching model. The device response, the energies and the timings are illustrative values, and it has not been compared against measured hardware or a circuit simulator such as SPICE.