PCM reference

Learning path

Three short lessons, each building on the one before. If you are new to this, go in order.

The signal chain in one line

Everything in the simulator sits somewhere on this path. The middle is analog. The two ends are converters to and from the digital world.

1. digital

   Input x

   0 to 1

   A number from the model or the previous layer.

2. converter

   DAC

   V = x × V_read

   Rounds the input and makes a voltage.

3. analog

   Word lines

   V_1 … V_M

   One voltage per row, all applied at once.

4. analog

   Cells

   I = V × G

   Each cell stores a weight as G and multiplies.

5. analog

   Bit lines

   I = Σ V × G

   The currents of a column add on the wire.

6. analog

   Subtract

   I⁺ − I⁻

   The pair gives a signed result.

7. converter

   ADC

   code → y

   Turns the current into an integer, then a number.

Key equations

Each one has a worked example with the simulator's default numbers (Gmin = 0.5 µS, Gmax = 50 µS) and a pointer to where you can see it. Equations 8, 9, 10, 12 and 13 describe this teaching model, not a measured device.

I = V × G      (G = 1 / R)

I_j = Σ_i  V_i × G_ij

V_i = x_i × V_read

level = round(|w| × (L − 1))
G = Gmin + level / (L − 1) × (Gmax − Gmin)
L = 2^bits

y = (I⁺ − I⁻) / (V_read × (Gmax − Gmin))

G⁺ only + reference column:
  level = round((w + 1)/2 × L),   G = Gmin + level/L × (Gmax − Gmin)
  G_ref = Gmin + (Gmax − Gmin)/2   (every row of the reference column)
  y = 2 × (I − I_ref) / (V_read × (Gmax − Gmin))

Unsigned, negatives clipped:
  level = round(max(w, 0) × L),   G = Gmin + level/L × (Gmax − Gmin)
  y = I / (V_read × (Gmax − Gmin))

step = R / (2^(b−1) − 1)
R = rows × ADC range

a_target = ln(G_target / Gmax) / ln(Gmin / Gmax)
pick V_n: the strongest SET whose nominal shrink factor f(V) is still ≥ a_target / a_n
if |G − G_target| ≤ tol × (Gmax − Gmin): stop
if G > G_target + tol: RESET (a = 1) and climb again

G(a) = Gmax × (Gmin / Gmax)^a             a = amorphous fraction, 0 to 1
T_peak = 300 + 162 × V² × (1 − e^(−t_p / 30 ns))   K
rate r = exp(−((T_peak − 700) / 130)²)   for 430 K < T_peak < 900 K, else 0
SET:   a ← a × exp(−r × t_p × f / 40 ns)
RESET: T_peak > 900 K melts the cell and the fast edge freezes it: a ← 1

SET pulse:    E = V² × t_p / R_h
RESET pulse:  E = (3.1 V)² × 20 ns / R_h
Verify read:  E = V_read² × G × t_read + E_ADC
(R_h = 5 kΩ heater)

E_crossbar = Σ V × I × t_read
           + inputs × E_DAC + columns × E_ADC
E_digital  = (M × N) × (E_MAC + E_fetch)
break-even = E_write / (E_digital − E_crossbar)

solved numerically (Gauss-Seidel)

G(t) = G(1 s) × t^(−ν)
ν = 0.005 + 0.095 × a

y_corrected = y × t^ν_ref        (ν_ref = 0.03 in the simulator)

Glossary

Type to filter the 48 terms by name or by anything in the definition.

Adaptive pulse

A write scheme where the controller picks each SET amplitude from how far the cell still has to go: strong pulses far away, gentle ones close by. The default write method in the simulator.

ADC (analog-to-digital converter)

Turns a bit-line current into an integer code. More bits give finer output steps. In the efficiency model each extra bit doubles the ADC's energy.

Amorphous and crystalline

Glass-like and ordered. The amorphous state resists current (low G) and the crystalline state conducts well (high G). The cell holds a mix of the two.

Amorphous dome, fraction a

The glassy cap over the heater in a mushroom cell. In this model its size is a, from 0 (no glass) to 1 (full dome), and G = Gmax × (Gmin / Gmax)^a.

Bit line (BL)

The wire that runs down a column and collects the currents of every cell in it. Its total current is the sum of V × G over the column.

Bit slicing (binary weighted encoding)

Storing each bit of a weight in its own pair of two-state cells and combining the bit planes with shifts and adds in digital logic. It uses more cells and more ADC conversions, but each cell only needs two well-separated states. The Cell encoding menu in Step 3 offers it.

Block erase

A RESET applied to a block of cells so that all of them start from the full-dome state, Gmin, before the SET climb begins.

Chalcogenide (GST)

The family of alloys used for PCM, for example germanium-antimony-tellurium (Ge₂Sb₂Te₅). They switch between glass and crystal in nanoseconds, which is why they are also used in rewritable optical discs.

Compute-in-memory (in-memory computing)

Doing arithmetic inside the memory array where the data is stored, instead of moving the data to a separate processor.

Conductance (G)

How easily a cell passes current. G = 1 / R, measured in siemens (S). The cells here sit between 0.5 and 50 µS, which is 2 MΩ down to 20 kΩ. Conductances on a shared wire simply add, which is why weights are stored as conductance and not as resistance.

Crossbar

A grid of word lines crossing bit lines, with one memory cell at every crossing.

Crystallization

SET: a longer, gentler pulse keeps the cell hot but below melting (best near 700 K here), so the glass slowly turns back into crystal and the dome shrinks. Each pulse shrinks it a bit more.

Cycle-to-cycle variation

The same cell responds a little differently to the same pulse each time it is written.

DAC (digital-to-analog converter)

Turns an input number into a voltage on a word line. The simulator rounds inputs to 2^b − 1 steps.

Device-to-device variation

Different cells respond differently to the same pulse, because no two domes form identically. The σ slider sets how large the spread is.

Differential pair (G⁺ / G⁻)

Two cells that together store one signed weight. The positive part goes in G⁺, the negative part in G⁻, and the read-out subtracts the two currents.

Drift compensation

Correcting for drift in the readout, for example with a single gain that grows with time. It works only as well as the cells share one ν.

Drift exponent (ν)

The power in the drift law. In this model ν = 0.005 + 0.095 × a, so nearly crystalline cells (small dome) drift little and mostly amorphous cells drift a lot.

Endurance

How many SET and RESET cycles a cell survives before its window shrinks or it stops switching. Step 1 has a write-cycles slider that shows it.

High-resistance state (HRS) and low-resistance state (LRS)

The two extremes of a cell. HRS is the lowest conductance (Gmin, full amorphous dome) and LRS is the highest (Gmax, no dome). Between them the cell can hold intermediate analog levels.

IR drop

Voltage lost along the resistance of the wires. Cells far from the drivers see less voltage, so their currents are lower than the ideal. The Wire R slider controls it and the simulator solves for it.

Joule heating

Heat from the current passing through the cell. PCM is programmed by it, so SET and RESET pulses are heat pulses as much as voltage pulses.

Kirchhoff's current law

The currents flowing into a point add up to the currents flowing out. It is why all the cell currents on one bit line sum into a single current.

Level (conductance level)

One of the 2^b discrete conductance values a cell is aimed at. Level k of L − 1 steps sits at Gmin + k / (L − 1) × (Gmax − Gmin).

Matrix-vector multiplication (MVM)

y = xᵀW: every output is the dot product of the input vector with one column of weights. It is the main operation inside neural-network layers.

Melt-quench

RESET: a short, strong pulse heats the cell past the melting point (900 K in this model) and the pulse edge is so fast that the melt freezes into glass instead of crystallizing.

Multiply-accumulate (MAC)

One multiplication added to a running total. A matrix-vector product is many MACs.

Mushroom cell

A common PCM layout: a narrow heater electrode under a layer of phase-change material, so the hottest spot, and the glassy dome, forms over the heater.

Neural network (NN)

A model built from layers. Each layer computes weighted sums of its inputs and then applies a simple nonlinear function. The weights are numbers learned during training. These lessons only need the weighted sum, which a crossbar computes in one read.

Non-volatile

Keeps its stored state with the power off.

Ohm's law

V = I × R, or equivalently I = V × G. It is the multiplication step in the crossbar.

On/off ratio (window)

Gmax / Gmin. With the defaults, 50 / 0.5 = 100. A wider window leaves more room between levels.

Open-loop write

Applying a fixed train of pulses without reading the cell back. It is cheap, but device variation lands directly in the stored weight.

Overshoot

A SET pulse that leaves the conductance above the target band. PCM has no gentle step down, so the cell must be RESET and written again.

Phase-change memory (PCM)

A memory cell made of a chalcogenide alloy that can be glass (amorphous, high resistance) or crystal (low resistance). Heat pulses switch it, and it keeps its state with the power off. It can hold a bit or, with intermediate dome sizes, a neural-network weight.

Program-and-verify (write-verify)

Writing in a loop: pulse, read back, compare with the target, and repeat until the cell is within tolerance or the pulses run out. In PCM an overshoot cannot be undone by another SET, so it costs a RESET and a new climb.

Quantization

Rounding to one of a limited set of values: inputs by the DAC, weights to conductance levels, outputs by the ADC.

Read disturb

A read at too high a voltage can heat the cell enough to change its state, so the read voltage is kept low.

Reference column

One extra column of cells, all at the middle conductance Gmid, shared by every output. Its current is subtracted from each output, so a single cell per weight can still stand for a negative weight.

RESET

A pulse that melts the cell and quenches it into glass. In this model it always returns the cell to the full dome and Gmin, so it is both the erase and the only way down.

Resistance drift (drift)

After the write the amorphous glass slowly relaxes and the conductance falls as a power law of time, G(t) = G(1 s) × t^(−ν). Steps 1, 2 and 3 each have a time slider that shows it.

SET

A pulse that crystallizes part of the dome and so raises the conductance. In PCM it comes in small steps and can only go up.

Sneak path

In a passive crossbar, current that finds a route through other cells instead of the selected one, which corrupts reads and writes. Transistors (1T1R) or selector devices suppress it. This simulator does not model sneak paths.

Tolerance

How close to the target counts as done in a verify loop, set as a percent of the Gmax − Gmin window.

Unsigned encoding (negatives clipped)

One cell per weight and no subtraction. A cell cannot be negative, so negative weights are stored as 0, and the Gmin leakage of every cell adds a small offset to each output.

Von Neumann bottleneck

The time and energy spent moving data between a separate memory and processor. Computing in the array avoids moving the weights.

Weight

A number the model learned. Here it runs from −1 to +1 and is stored as conductance in one or two cells.

Word line (WL)

The wire that runs along a row and carries one input voltage to every cell in that row.

No term matches. Try a shorter word.

Symbols and units

The defaults are the values the simulator starts with.

1 µS = 10⁻⁶ siemens, which is a resistance of 1 MΩ. 50 µS is 20 kΩ. A voltage in volts times a conductance in µS gives a current in µA. A voltage times a current in µA times a time in ns gives energy in fJ (1,000 fJ = 1 pJ). Volts² over kΩ times ns gives pJ directly.

What each setting does

Each row says what happens when you raise the setting. The numbers are the RMS output error (or the write cost) measured on the simulator’s default 4 × 4 example with 10% variation and adaptive program-and-verify writing, changing one setting at a time. They are a guide to the direction and size of each effect, and will shift if you change other settings or the simulator is updated.

Array and signal chain

Writing the weights

Efficiency panel

Common questions

Further reading

Start with the PCM review by Le Gallo and Sebastian and the 2023 chip paper. The others are the original sources for ideas used in these pages. The device numbers in the simulator are illustrative, not taken from these papers. Check each publisher page for the final details.

1. Wong, H.-S. P., Raoux, S., Kim, S., Liang, J., Reifenberg, J. P., Rajendran, B., Asheghi, M. & Goodson, K. E. Phase change memory. Proceedings of the IEEE 98, 2201–2227 (2010). IEEE Xplore
   A review of the device physics, the materials, the scaling and the reliability of PCM, with a focus on memory use.
2. Raoux, S. et al. Phase-change random access memory: a scalable technology. IBM Journal of Research and Development 52 (2008). IEEE Xplore
   Explains the mushroom cell, the SET and RESET operations and why the technology scales to small sizes.
3. Wuttig, M. & Yamada, N. Phase-change materials for rewriteable data storage. Nature Materials 6, 824–832 (2007). doi:10.1038/nmat2009
   Why some alloys switch between glass and crystal so quickly, and how the same materials are used in optical discs and in memory.
4. Le Gallo, M. & Sebastian, A. An overview of phase-change memory device physics. Journal of Physics D: Applied Physics (2020). doi:10.1088/1361-6463/ab7794
   A recent overview of threshold switching, crystallization, resistance drift and noise, written with in-memory computing in mind.
5. Burr, G. W. et al. Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses) using phase-change memory as the synaptic weight element. IEEE Transactions on Electron Devices (2015). doi:10.1109/TED.2015.2439635
   An early experiment that stored neural-network weights in a pair of PCM cells each, and what it took to tolerate their imperfections.
6. Le Gallo, M. et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nature Electronics 6, 680–693 (2023). doi:10.1038/s41928-023-01010-1
   A chip that does what the crossbar simulator in Step 3 models, built with PCM weights, and the drift and noise problems it had to handle.
7. Ielmini, D. and Wong, H.-S. P. "In-memory computing with resistive switching devices." Nature Electronics 1, 333–343 (2018). Link
   A broad review of crossbar computing with resistive devices, including matrix-vector multiplication.
8. Alibart, F., Gao, L., Hoskins, B. D. and Strukov, D. B. "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm." Nanotechnology 23, 075201 (2012). Link
   The write-and-verify idea of Step 2, applied to real (memristive) devices.
9. Sebastian, A. et al. "Memory devices and applications for in-memory computing." Nature Nanotechnology 15, 529–544 (2020).
   Survey of memory devices used for computing. Search the title to find the publisher page.
10. Hu, M. et al. "Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication." Design Automation Conference (DAC), 2016.
    Matrix-vector multiplication on a memristor crossbar and how it is programmed.