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In a ReRAM array (the crossbar of Step 3), the weights are not stored as bits in a file. Each one is a conductance, and a cell has to be pushed to it with electrical pulses and checked. Follow one weight through the six steps below, from a number on a slider to a conductance inside a cell.
Short answer: no, a cell does not have four connections. A ReRAM cell has two terminals, a top electrode and a bottom electrode, and SET, RESET and read all use those same two. They are not separate wires. They are the same two terminals driven differently: SET is a pulse above the switching threshold with one polarity, RESET is a pulse above it with the opposite polarity, and a read is a small voltage (0.2 V) below it. What changes between operations is what the line drivers at the edge of the array put on the lines.
Only two kinds of wires. A word line (row) touches the top electrodes of every cell in the row, and a bit line (column) touches the bottom electrodes of every cell in the column. Each cell sits at one crossing, so it has exactly those two connections. This is the array of Step 3.
Each cell gets an access transistor. The word line now goes to the transistor gate and only picks the cell. The bit line (BL) goes to the top electrode and the source line (SL), through the transistor, to the bottom electrode. BL and SL carry the pulse and decide its polarity.
The word line is the wire on the top electrode and the bit line is the wire on the bottom electrode. There is no third wire for SET or RESET: swapping which of the two lines is high flips the polarity across the cell. Current flows from the higher line to the lower one.
Try it. Pick the operation, the wiring and the cell (click a cell in the drawing, or use the menus), and watch what every line is set to.
There are none. In the passive crossbar the SET pulse is a positive voltage between a word line and a bit line, and the RESET pulse is the same two lines with the voltages swapped, so the cell sees a negative voltage. In the 1T1R array the roles of BL and SL swap. The driver circuits at the edge of the array decide which polarity goes where, and the cell only sees the voltage across its two electrodes.
Not in the array drawn here. A read uses the same lines at a small voltage that is below the switching threshold, and the current of the bit line (the column) is measured by a sense amplifier or converter at the end of the column. In the compute mode of Step 3, every word line is driven at once with an input voltage and each bit line adds up the currents of its whole column, so that one read gives a dot product.
The two cells of one weight sit on the same word line and in two neighbouring columns, so one weight uses one row and two bit lines. The word line carries the input voltage to both, and the converter subtracts the two column currents. Writing G⁺ and G⁻ uses the same SET and RESET wiring as above, applied to one column at a time.
The wires are shared, so the count grows with the edge of the array and not with the number of cells. An R × C passive crossbar needs R + C lines (6 for the 3 × 3 above), and a 1T1R array needs R + 2C in this layout (9 for 3 × 3), because every column carries both a BL and an SL. Names and layouts vary between papers and chips; some designs run the source line along the row instead of along the column.
This is a schematic of the biasing, not a circuit model. In a passive crossbar the unselected cells also let current sneak around through unselected paths, so real arrays add a selector or a transistor (the 1T1R case). The 0.8 V switching threshold is the one used on the rest of this page. The ReRAM basics page has a shorter version of this drawing in section 2B.
A conductance cannot be negative, but a weight can. The positive part goes into the G⁺ cell and the negative part into the G⁻ cell, and the other cell rests at Gmin. The read-out subtracts the two currents, so Gmin cancels.
3 bits gives 8 levels, which is 7 steps between Gmin and Gmax. 0.62 × 7 = 4.34 rounds to level 4, and level 4 is worth 4 / 7 = 0.571. The loss of 0.049 is rounding, and it happens before any pulse is sent. More bits make the steps smaller but pack the levels closer together.
The same pulse moves different cells by different amounts, and even the same cell by different amounts each time. Switch to "Open loop" in step 5 and press "Different cell" a few times to see the spread. Reading back lets the controller stop each cell when it is close enough.
More pulses and more reads, so more time and energy per weight, and sometimes the loop cannot land inside a very narrow band and runs out of pulses. A looser tolerance is cheaper but leaves a bigger error in every weight. Try ±0.5% and ±10% in step 5.
Only the input voltages. The conductances stay where they were written, so the cost of writing is paid once and shared by every multiply that reuses those weights. The efficiency panel in Step 3 has a "Weight reuse" slider for this.
Step 3 is the crossbar simulator. It stores a whole matrix this way, repeating this loop for every cell, and shows the pulse count and total write cost, then multiplies with it. The reference page collects the equations, terms and settings used in all three steps.
The pulse voltages, pulse counts and conductances on this page come from an illustrative model, not from a real device. These papers describe write-and-verify on real devices.
The full, grouped list is at the end of the crossbar simulator. Links can change, so searching the title and DOI always works.